1. Field of the Invention
The present invention relates to an improved technique for connecting integrated circuit transistors to the doped semiconductor regions in which they are formed, and the integrated circuits formed thereby.
2. Description of the Prior Art
In the design of integrated circuits employing field effect transistors, it is frequently necessary to electrically connect a source electrode to the doped semiconductor region in which it is formed. A doped semiconductor region in which transistors are formed, and having a different doping level or type than the semiconductor substrate (or epitaxial layer thereon) in which it is formed, is referred to as a "tub". For example, in complementary field effect device technology, (e.g., CMOS), the p-channel transistors may be formed in a n-tube connected to the positive power supply voltage (V.sub.DD), and the n-channel transistors may be formed in a p-tub connected to the negative power supply voltage (V.sub.SS). The sources of the p- and n-channel transistors are then electrically connected to their respective tubs, in order to receive their respective power supply voltages. One process for forming both p-tubs and n-tubs is disclosed in U.S. Pat. No. 4,435,896 coassigned with the present invention, with others also being known in the art. Furthermore, in some processes, only a single type of tub region is present, being of the opposite conductivity type as the substrate region in which it is formed. Then, the transistors of one conductivity type are formed in the tubs, and the transistors of the opposite conductivity type are formed in the surrounding substrate region. In either the twin tub or the single tub case, the electrical connection between the source and the tub in which it is formed is referred to as a "tub tie".
In order to provide a tub-tie, the prior art provides for opening two contact windows in the dielectric layers overlying both the source region and an adjacent portion of the tub. A low-resistance conductive link, typically aluminum, is then deposited so as to overlie the dielectric material between the windows, and extends into the windows to contact both the source and tub regions. However, this technique requires that space on the integrated circuit be provided for the two contact windows, which is typically greater than the space otherwise required for the device fabrication. An alternative prior art technique utilizes one large contact window, rather than two normal size windows. The large single window provides an opening over both the source and tub regions. A single conductive plug, typically aluminum, is then deposited into the window, thereby electrically connecting the two regions at the bottom of the window. However, this has the disadvantage that the window must be made large enough to ensure that it overlaps both the source and substrate. Typically more area is again required for layout of the circuit than if the tub tie were not present. Furthermore, the nonstandard size window complicates the use of computer aided design layout techniques. Therefore, the use of a large single contact window is usually reserved for hand-packed circuit layouts. In the foregoing techniques, to reduce the contact resistance, a more highly doped tub contact region is formed in the tub, before forming the tub tie. For example, a n+ doped region is provided in an n tub, and the contact window opened over the tub contact region, with the tub tie conductor then being deposited.
It is known to decrease the contact resistance to source/drain regions, as well as to the gate electrode, by forming a silicide surface layer thereon. This may be accomplished in a single operation by the so-called "salicide" process, by reacting a refractory metal (e.g., titanium) with the exposed silicon of the source/drain regions, as well as the polysilicon gate electrode; see, for example, "Titanium disilicide self-aligned source/drain+gate technology", C. K. Lau et al, IEDM Technical Digest, pp. 714-717 (1982).